AK7735EQ Datasheet, PDF (52/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
5. Input/Output Serial Interface Format
5-1. Data Clocks
The AK7735 has three LRCK/BICK pins that are input/output switchable to interface with external
equipment. MSNx bit controls master and slave modes of LRCKx/BICKx pins (Table 14). DCFx[2:0] bits
control each clock format of these pins independently. If LRCKx/BICKx pins are configured as slave
mode, set DCFx[2:0] bits according to the input clock. If LRCKx/BICKx pins are configured as master
mode, the output clock format is selected by DCFx[2:0] bits.
Mode
0
1
2
3
DCFx[2]
0
1
1
1
DCFx[1] DCFx[0]
Clock Format
0
0
I²S Mode
0
1
DSP Mode
1
0
PCM Short Frame
1
1
PCM Long Frame
Table 21. AK7735 Data Clock Format
BCKPx bit controls the relationship of BICKx and LRCKx edges.
(default)
BCKPx bit BICKx edge referenced to LRCKx start edge
0
Falling Edge
(default)
1
Rising Edge
Table 22. Relationship of BICKx and LRCKx Edges
016014707-E-00
- 52 -
2016/12