AK7735EQ Datasheet, PDF (82/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
4-2. RAM Write Timing during RUN
These operations described below are to rewrite the Coefficient RAM (CRAM) and Offset REG (OFREG)
during RUN. Data writing is executed in two steps; write preparation and write execution. The written
data can be confirmed by reading the write preparation data.
(1) Write Preparation
After inputting the assigned command code (8 bits) to select the number of data from 1 to 16, input the
starting address of write (16 bits) and the number of data assigned by command code in this order.
(2) Write Preparation Data Confirmation
After write preparation, prepared data for writing can be confirmed. Address and Data are read in this
order by write preparation data confirmation command “24H/26H” (CRAM) or “25H/27H” (OFREG). The
data will be “0x000001” when reading more than write preparation data. Execute write preparation again
when the address and data are disturbed by external noise.
(3) Write Execution
Upon completion of the above operation, execute a RAM write during RUN by inputting the
corresponding command code and address (16 bits, all “0”) in this order.
Note
* 65. Execute Write Preparation and Write Preparation Data Confirmation before Write Execution. A
Write Preparation Data Confirmation sequence can be skipped, but a malfunction occurs when
executing Write Execution to RAM without a Write Preparation sequence. Access operation by a
microcontroller is prohibited until RDY changes to “H”.
Write modification of the RAM content is executed whenever the RAM address for modification is
accessed. For example, when 5 data are written, from RAM address “10”, it is executed as shown below.
RAM execution address 7 8 9 10 11 13 16 11 12 13 14 15
↓↓
↓↓↓
Write execution position
○ ○ wait
○○○
Note
* 66. Address “13” is not executed until rewriting address “12”.
DxRESETN bit= “1”
(x= 1, 2)
CSN
SCLK
SI
don’tcare Command _{Address DATA0}
(L/H)
Code
DATA1
DATAn-1 DATAn
(Ex.) When # of DATA is 4
CRAM Command Code 0x83
OFREG Command Code 0x93
don’tcare
(L/H)
RDY = “H”
CRAM 0x80(# of DATA: 1)~0x8F(# of DATA: 16)
OFREG 0x90(# of DATA: 1)~0x9F(# of DATA: 16)
Figure 57. CRAM/OFREG Write Preparation (SPI)
016014707-E-00
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2016/12