AK7735EQ Datasheet, PDF (43/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
3. Sampling Frequency Setting of ADC and DAC Blocks
Available sampling modes for analog block of the AK7735 are shown below. Sampling frequency mode
is set by FSMODE[4:0] bits. ADC1 can be operated by a different sampling frequency from ADC2, DAC1
and DAC2.
Mode FSMODE[4:0] bits ADC2, DAC1, DAC2
ADC1
0
00000
8kHz
8kHz (default)
1
00001
12kHz
12kHz
2
00010
16kHz
16kHz
3
00011
24kHz
24kHz
4
00100
32kHz
32kHz
5
00101
32kHz
16kHz
6
00110
32kHz
8kHz
7
00111
48kHz
48kHz
8
01000
48kHz
24kHz
9
01001
48kHz
16kHz
10
01010
48kHz
8kHz
11
01011
96kHz
96kHz
12
01100
96kHz
48kHz
13
01101
96kHz
32kHz
14
01110
96kHz
24kHz
15
01111
96kHz
16kHz
16
10000
96kHz
8kHz
17
10001
192kHz
192kHz
18
10010
192kHz
96kHz
19
10011
192kHz
48kHz
20
10100
192kHz
32kHz
21
10101
192kHz
16kHz
Others
N/A
N/A
N/A
Table 12. Sampling Frequency Settings of ADC and DAC Blocks (fs=48kHz base, N/A: Not Available)
Clock Sync Domain of the ADC1 (SDADC1) is selected by SDADC1[2:0] bits and Clock Sync Domain of
the ADC2, DAC1 and DAC2 (SDCODEC) is selected by SDCODEC[2:0] bits (Table 18).
The sampling frequency of LRCKSDx for SDADC1 and the sampling frequency of the ADC1 should be
the same. The sampling frequency of LRCKSDx for SDCODEC and the sampling frequency of the
ADC2, DAC1 and DAC2 should also be the same. SDADC1 and SDCODEC must be synchronized with
PLLMCLK.
Set SDADC1[2:0] bits to “000” (reference clock is fixed to “L”) when not using the ADC1. In the same
manner, SDCODEC[2:0] bits should be set to “000” when not using the ADC2, DAC1 and DAC2.
016014707-E-00
- 43 -
2016/12