AK7735EQ Datasheet, PDF (72/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
1-1. Write
Command
80H ~ 8FH
90H ~ 9FH
A2H
A3H
A4H
A5H
B2H
B3H
B4H
B5H
B8H
B9H
C0H
F2H
F4H
F5H
Address
16bit
16bit
16bit
16bit
16bit
16bit
16bit
16bit
16bit
16bit
16bit
16bit
16bit
16bit
16bit
16bit
Data Length
24bit x n
24bit x n
-
-
-
-
24bit x n
24bit x n
24bit x n
24bit x n
40bit x n
40bit x n
8bit x n
16bit
8bit
8bit
Description
Write preparation to CRAM of DSP1/DSP2 during RUN
(80H: write 1data, 81H: write 2data, ----, 8FH: write 16data) If
the actual amount of write operations exceeds the defined
amount, the data will be ignored.
Write preparation to OFREG of DSP1/DSP2 during RUN
(90H: write 1data, 91H: write 2data, ----, 9FH: write 16data) If
the actual amount of write operations exceeds the defined
amount, the data will be ignored.
Write execution to OFREG of DSP1 during RUN.
0 address should be written.
Write execution to OFREG of DSP2 during RUN.
0 address should be written.
Write execution to CRAM of DSP1 during RUN.
0 address should be written.
Write execution to CRAM of DSP2 during RUN.
0 address should be written.
Write operation to OFREG of DSP1 (during DSP reset)
Write operation to OFREG of DSP2 (during DSP reset)
Write operation to CRAM of DSP1 (during DSP reset)
Write operation to CRAM of DSP2 (during DSP reset)
Write operation to PRAM of DSP1 (during DSP reset)
Write operation to PRAM of DSP2 (during DSP reset)
Sequential Control Register Write
CRC Result Write
0 address should be written.
Write operation of DSP1 JX code
0 address should be written.
Write operation of DSP2 JX code
0 address should be written.
The data length is defined by the command code which specifies the area to be accessed. Writing other
than the above-mentioned command code is prohibited.
016014707-E-00
- 72 -
2016/12