AK7735EQ Datasheet, PDF (112/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
6. SRC Lock
The STO pin outputs the SRC status by setting SRCLOCKEx bit (x= 1, 2) to “1”. The STO pin outputs “H”
if the SRC is locked, and outputs “L” when the SRC is unlocked or when the SRC is in reset state
(PMSRCx bit = “0”).
7. Group Delay when using SRCs in the Same Rate
When SRC1 and SRC2 use the same Sync Domain for input clock (FSI) and the same Sync Domain for
output clock (FSO), a maximum 2xFSO mismatch of group delay may occur between them. This group
delay mismatch can be avoided by setting PMSRC1 and PMSRC2 bits to “1” simultaneously after setting
SRCPHGR bit to “1”. A click noise may occur if PMSRC1/2 bits are not set to “1” at the same time when
SRCPHGR bit is “1”.
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2016/12