AK7735EQ Datasheet, PDF (55/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
5-3. Input/ Output Interface Format
The AK7735 has four digital input ports and four digital output ports. The data format can be set
independently.
The input data format is determined by a combination of DISLx[1:0], DIEDGENx, DILSBEx and
DIDLx[1:0] bits settings (x=1~4). The output data format is determined by a combination of DOSLx[1:0],
DOEDGENx, DOLSBEx and DODLx[1:0] bits settings (x=1~4).
DISLx[1:0] bits / DOSLx[1:0] bits (x=1~4) control input/output data slot length.
Mode
DISLx[1] bit DISLx[0] bit
DOSLx[1] bit DOSLx[0] bit
Slot Length
0
0
0
24bit
1
0
1
20bit
2
1
0
16bit
3
1
1
32bit
Table 23. Slot Length Setting of Input/Output Data
(default)
DIDLx[1:0] bits / DODLx[1:0] bits (x=1~4) control input/output audio data word length.
Mode
DIDLx[1] bit DIDLx[0] bit
DODLx[1] bit DODLx[0] bit
Word Length
0
0
0
24bit
(default)
1
0
1
20bit
2
1
0
16bit
3
1
1
32bit
Table 24. Word Length Setting of Input/Output Audio Data
DILSBEx bit/ DOLSBEx bit (x=1~4) select the audio data format of a slot.
DILSBEx bit
DOLSBEx bit
Slot Data Format
0
MSB First
1
LSB First
Table 25. Slot Data Format Setting
(default)
DIEDGENx bit / DOEDGENx bit (x=1~4) select data transmission start timing of the data after second
channel
DIEDGENx bit
DOEDGENx bit
Start Timing
0
LRCK Edge Basis
(default)
1
Slot Length Basis
Table 26. Data Transmission Start Timing Selection of The Data After Second Channel
If the data transmitting timing is set to Slot length basis, the next channel’s data is transmitted
immediately without waiting a LRCK edge after transmitted one slot data (Figure 29~ Figure 33).
If the data transmitting timing is set to LRCK edge basis, the next channel’s data will not be transmitted
until a LRCK edge even finished transmitting one slot data (Figure 26 ~ Figure 28).
016014707-E-00
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2016/12