AK7735EQ Datasheet, PDF (117/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
Addr Register Name
000B Sync Domain M/S Setting
R/W
Default
D7
D6
D5
D4
D3
D2
0
0
0
0
0
MSN3
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
MSN3: Slave/Master Mode Setting of LRCKSD3/BICKSD3 (Table 7, Table 14)
0: Slave Mode (default)
1: Master Mode
MSN2: Slave/Master Mode Setting of LRCKSD2/BICKSD2 (Table 7, Table 14)
0: Slave Mode (default)
1: Master Mode
MSN1: Slave/Master Mode Setting of LRCKSD1/BICKSD1 (Table 7, Table 14)
0: Slave Mode (default)
1: Master Mode
D1
MSN2
R/W
0
D0
MSN1
R/W
0
Addr Register Name
000D CLKO Output Setting
R/W
Default
D7
D6
D5
D4
D3
0
0
0
0
CLKOE
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
CLKOE: Output Enable of the CLKO Pin
0: CLKO pin = “L” (default)
1: CLKO pin Output Enable
CLKOSEL[2:0]: CLKO Pin Output Clock Frequency Setting (Table 13)
Default: “000” (12.288MHz / 11.2896MHz)
D2
D1
D0
CLKOSEL[2:0]
R/W
000
016014707-E-00
- 117 -
2016/12