AK7735EQ Datasheet, PDF (71/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
■ SPI Interface
1. Configuration
The access format consists of Command code (8bits) + Address (16bits) + Data (MSB first).
Command code
Address
Data
Bit Length
8
16
Mentioned in
later section
Description
MSB bit is an R/W flag. The following 7 bits indicate access area such
as PRAM/ CRAM/Registers.
Address is fixed to 16bits.
Read/Write Data
Table 33. μP Interface Format
Write
CSN
SCLK
SI
don’tcare
(L/H)
Command Code (8bit)
Address (16bit)
Data (write)
SO
Hi-Z
Echo Back
Figure 50. SPI Interface Timing (Write)
Read (Except Read Operation during Run）
CSN
don’tcare
(L/H)
Hi-Z
SCLK
SI
don’tcare
(L/H)
Command Code (8bit)
SO
Hi-Z
Address (16bit)
Echo Back
Data (Read)
don’tcare
(L/H)
Hi-Z
Figure 51. SPI Interface Timing (Read) (Except Command 24H, 25H, 26H and 27H)
Read (during Run)
CSN
SCLK
SI
don’tcare
(L/H)
Command Code (8bit)
SO
Hi-Z
Address (16bit)
Data (Read)
Figure 52. SPI Interface Timing (Read) (Command 24H, 25H, 26H and 27H)
don’tcare
(L/H)
Hi-Z
016014707-E-00
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2016/12