AK7735EQ Datasheet, PDF (118/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
Addr
000F
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
001A
001B
Register Name
Sync Domain Select 1
Sync Domain Select 2
Sync Domain Select 3
Sync Domain Select 4
Sync Domain Select 5
Sync Domain Select 6
Sync Domain Select 7
Sync Domain Select 8
Sync Domain Select 9
Sync Domain Select 10
Sync Domain Select 11
Sync Domain Select 12
Sync Domain Select 13
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
SDBCK1[2:0]
0
SDBCK2[2:0]
0
SDBCK3[2:0]
0
0
0
0
0
SDDSP1[2:0]
0
SDDSP2[2:0]
0
SDDSP1O1[2:0]
SDDSP1O2[2:0]
0
SDDSP1O3[2:0]
0
SDDSP1O4[2:0]
0
SDDSP1O5[2:0]
0
SDDSP1O6[2:0]
0
SDDSP2O1[2:0]
0
SDDSP2O2[2:0]
0
SDDSP2O3[2:0]
0
SDDSP2O4[2:0]
0
SDDSP2O5[2:0]
0
SDDSP2O6[2:0]
0
SDSRCO1[2:0
0
SDSRCO2[2:0
SDADC1[2:0]
0
SDCODEC[2:0]
0
SDDO1[2:0]
0
SDDO1[2:0]
0
SDDO3[2:0]
0
SDDO4[2:0]
R/W
R/W
R/W
R/W
0
000
0
000
SDxxxx[2:0]: Sync Domain Setting of Input/Output Port for Data and Clocks (Table 19, Table 20)
Default: “000” (TieLow)
Addr Register Name
001C External Clock Domain Select
R/W
Default
D7
D6
EXBCK4[1:0]
R/W
00
D5
D4
EXBCK3[1:0]
R/W
00
D3
D2
EXBCK2[1:0]
R/W
00
EXBCK4[1:0]: Synchronizing BICK/LRCK Pin Setting with SDIN4 Pin (Table 16)
Default: “00” (TieLow)
EXBCK3[1:0]: Synchronizing BICK/LRCK Pin Setting with SDIN3 Pin (Table 16)
Default: “00” (TieLow)
EXBCK2[1:0]: Synchronizing BICK/LRCK Pin Setting with SDIN2 Pin (Table 16)
Default: “00” (TieLow)
EXBCK1[1:0]: Synchronizing BICK/LRCK Pin Setting with SDIN1 Pin (Table 16)
Default: “00” (TieLow)
D1
D0
EXBCK1[1:0]
R/W
00
016014707-E-00
- 118 -
2016/12