AK7735EQ Datasheet, PDF (78/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
3-1-4. Read Operation during RUN
(1) CRAM Write Preparation Read (during RUN)
Field
Write data
(1) COMMAND Code 0x24 (DSP1) / 0x26 (DSP2)
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
Readout data
0 0 0 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
D23~D16
D15~D8
D7~D0
(2) OFREG Write Preparation Read (during RUN)
Field
Write data
(1) COMMAND Code 0x25 (DSP1) / 0x27 (DSP2)
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
Readout data
00000000
0 0 A5 A4 A3 A2 A1 A0
00000000
0 0 D13 D12 D11 D10 D9 D8
D7~D0
(3) MIR Register Read (during RUN)
Field
Write data
Readout data
(1) COMMAND Code 0x76 (DSP1) / 0x77 (DSP2)
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
(4) DATA1
D27~D20
(5) DATA2
D19~D12
(6) DATA3
D11~D4
(7) DATA4
D3 D2 D1 D0 (flag3) (flag2) (flag1) (flag0)
MIR register sequential read for DSP1/DSP2.
Max 8 data (32 bytes) may be read continuously.
The data is 28-bit MSB justified. Lower 4 bits are validity flags; the data is
valid only when all flags are zero.
016014707-E-00
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2016/12