AK7735EQ Datasheet, PDF (47/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
SDIN1pin
SDIN2pin
SDIN3pin
SDIN4pin
SDIN1
SDIN1
SDIN2
SDIN1
SDIN3
SDIN1
SDIN4
SDIN1
SDOUT1 pin
SDOUT2 pin
SDOUT3 pin
SDOUT4 pin
SDOUT1
SDOUT1～5
SDOUT2
SDOUT1～5
SDOUT3
SDOUT1～5
SDOUT4
SDOUT1～5
SRC1
SRC2
SDO^SRU^CIT¹1～
SRCO1
SD5IN1
SDO^SRU^CIT²1～
SRCO2
SD5IN1
ALL0
SDIN1
DIN1
SD_DO_OU_UT_T1₁～
SDS_DO^DD_OIU^N5I_U^N2T_T¹¹₂～
SDS_DO^DD_OIU^N5I_U^N3T_T¹¹₃～
SDS_DO^DD_OIU^N5I_U^N4T_T¹¹₄～
SDS_DO^DD_OIU^N5I_U^N5T_T¹¹₅～
SDS_DO^DD_OIU^N5I_U^N6T_T¹¹₆～
SDIN1
5
DIN1
SD_DO_OU_UT_T1₁～
SDS_DDOD_OIU^N5I_U^N2T_T¹¹₂～
SDS_DDOD_OIU^N5I_U^N3T_T¹¹₃～
SDS_DO^DD_OIU^N5I_U^N4T_T¹¹₄～
SDS_DO^DD_OIU^N5I_U^N5T_T¹¹₅～
SDS_DDOD_OIU^N5I_U^N6T_T¹¹₆～
SDIN1
5
ADC1
SDIN1
ADC2
SDIN1
DSP1
DSP2
ADC1
ADC2
: Input Port
SDIN1
SDOUT1～ ^{: Output Port}
5
DAC1
SDOUT1～
DA5C2
SDOUT1～
Serial Data Bus (Stereo 32bit)⁵
DAC1
DAC2
Figure 17. AK7735 Audio Data Path
2. Data Bus Group Delay
When the input and output ports with the same sampling frequency are connected via data bus, group
delay of 2/fs occurs in total as audio data will have 1/fs group delay at each input and output port of the
data bus (fs is the sampling frequency of the sync domain of the input and output ports).
Therefore, this group delay will increase as the number of times that the data goes through the data path
increases.
In the example of Figure 16, 2/fs (fs=8kHz) group delay occurs when inputting the SDIN1 data to SRC
via data bus and another 2/fs (fs=48kHz) group delay occurs when inputting the SRC1 output data to
DAC1 via data bus.
016014707-E-00
- 47 -
2016/12