AK7735EQ Datasheet, PDF (109/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
2. SRC Input/Output
Input sources of SRC1~2 are selected by SELSRCI1[5:0] and SELSRCI2[5:0] bits (Table 19, Table 20).
The input clock sync domains are inherited from the input data. The output clock sync domains are set
by SDSRCO1[2:0] and SDSRCO2[2:0] bits (Table 19, Table 20). Then the output data is sent to the data
bus.
3. SRC Soft Mute
The SRC1 and SRC2 have soft mute function independently.
3-1. Manual Mode
When SMUTEx bit (x=1, 2) is set to “1”, the SRC output data are attenuated to  in 1024 FSO cycles.
When the SMUTEx bit is set to “0”, the mute is cancelled and the output attenuation level gradually
changes to 0dB in 1024 FSO cycles. If the soft mute is cancelled before mute state, the attenuation is
discontinued and the attenuation level returns to 0dB by the same cycles. The soft mute is effective for
changing the signal source without stopping the signal.
SMUTEx bit
0dB
Attenuation Level
at SRCOx
-dB
(1)
(3)
(2)
Figure 77. Soft Mute Manual Mode
(1) SMUTEx bit (x=1, 2) = “0”→“1”: The output data is attenuated to  during 1024 FSO cycles.
(2) SMUTEx bit (x=1, 2) =“1”→“0”: The output attenuation level gradually changes to 0dB from  in
1024 FSO cycles.
(3) If the soft mute is cancelled within 1024 FSO cycles, the attenuation is discontinued and the
attenuation level returns to 0dB by the same number of clock cycles.
016014707-E-00
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2016/12