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AK7735EQ Datasheet, PDF (44/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC
[AK7735]
4. Master Clock Output Setting
The master clock output frequency setting of the CLKO pin is controlled by CLKOSEL[2:0] bits.
Mode
0
1
2
3
4
5
others
CLKOSEL[2:0] bits
Output Frequency Output Frequency
(fs=48kHz base) (fs=44.1kHz base)
000
12.288MHz
11.2896MHz
001
24.576MHz
22.5792MHz
010
8.192MHz
7.5264MHz
011
6.144MHz
5.6448MHz
100
4.096MHz
3.7632MHz
101
2.048MHz
1.8816MHz
N/A
N/A
N/A
Table 13. CLKO Output Frequency Setting (N/A: Not Available)
(default)
5. SDINx/BICKx/LRCKx pin Setting
The AK7735 has three BICK/LRCK pins and they are independent each other.
MSNx bit selects Master/Slave mode setting of the BICKx pin and the LRCKx pin (x=1~3). (Table 14)
MSNx bit (x=1~3)
BICKx pin, LRCKx pin
0
Slave Mode (Input)
(default)
1
Master Mode (Output)
Table 14. BICKx/LRCKx Pin Mode Selection
Note
* 50. Set MSNx bit to “0” when using the BICKx pin as PLL reference clock input pin.
When BICKx/LRCKx (x=1~3) pins are set to slave mode, the reference clocks of Clock Sync Domain x
are the clocks from BICKx/LRCKx pins (Table 7). When BICKx/LRCKx pins are set to master mode, the
output clocks of the BICKx/LRCKx pins can be selected from four Sync Domains by SDBCKx[2:0] bits
(x= 1~3). (Table 15)
MSNx bit SDBCKx[2:0] bits BICKx pin/LRCKx pin
1
000
TieLow
(default)
1
001
BICKSD1, LRCKSD1
1
010
BICKSD2, LRCKSD2
1
011
BICKSD3, LRCKSD3
1
100
BICKSD4, LRCKSD4
1
Others
N/A
Table 15. Clock Sync Domain Setting of BICKx/LRCKx Pins in Master Mode (N/A: Not Available)
Note
* 51. SDBCKx[2:0] bits can be in the default setting “000” (TIeLow) when BICKx pin/LRCKx pin (x=1~3)
are in slave mode.
The AK7735 has four serial data input ports (SDINx pin). Synchronizing clock of SDINx pin can be
selected from three BICKx/LRCKx pins by EXBCKx[1:0] bits.
EXBCKx[1:0] bits BICK/LRCK Synchronizing with SDINx Pin
00
TieLow
(default)
01
BICK1 pin, LRCK1 pin
10
BICK2 pin, LRCK2 pin
11
BICK3 pin, LRCK3 pin
Table 16. BICK/LRCK Setting Synchronizing with SDINx Pin
016014707-E-00
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2016/12