AK7735EQ Datasheet, PDF (31/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
11. Switching Characateristics
■ System Clock
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
AVSS=DVSS1=DVSS2=DVSS3=0V; C_L=20pF)
Parameter
Symbol
Min.
Typ.
Max.
XTI Input Timing
a) X’tal Oscillator
Input Frequency
fXTI
11.2896
18.432
b) XTI Clock Input
Duty Cycle
40
50
60
Input Frequency
fXTI
0.256
24.576
CLKO Output Timing
Output Frequency
fCLKO
2.048
24.576
Duty Cycle
dCLKO
50
LRCK/BICK Input Timing (Slave Mode)
LRCK Input Timing
Frequency
fs
8
192
BICK Input Timing
Frequency * 43
fBCLK
0.256
24.576
Pulse Width Low
tBCLKL 0.4 / fBCLK
Pulse Width High
tBCLKH 0.4 / fBCLK
LRCK/BICK Output Timing (PLL Master Mode)
LRCK Output Timing
Frequency
fs
8
192
Pulse Width High
PCM Mode
Except PCM Mode
tLRCKH
tLRCKH
1/fBCLK
50
BICK Output Timing
Frequency * 43
Duty
fBCLK
dBCLK
0.256
24.576
50
Note
* 43. Required to meet the following expression: fBCLK ≥ 2 x fs x (Input/Output Data Length).
Unit
MHz
%
MHz
MHz
%
kHz
MHz
ns
ns
kHz
ns
%
MHz
%
■ Power Down
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
AVSS=DVSS1=DVSS2=DVSS3=0V)
Parameter
Symbol Min.
Typ. Max.
Unit
PDN Pulse Width * 44
tRST
600
ns
Note
* 44. The PDN pin must be “L” when power up the AK7735.
PDN
tRST
VIL1
Figure 3. Reset Timing
016014707-E-00
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2016/12