AK7735EQ Datasheet, PDF (56/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
5-3-1. Stereo Mode
AK7735 supports stereo mode. The BICKx pin should be set to arbitrary frequency more than “word
length x 2fs” when DIEDGENx bit = “0”. The BICKx pin should be set to arbitrary frequency more than
“slot length x 2fs” when DIEDGENx bit = “1”. BICK clock is supported up to 256fs (Max.24.576MHz).
The SDINx input pins of the AK7735 support stereo input mode. Two slots data input is available for
each pin. A source address is assigned to each SDINx input pin when using stereo input mode (Table
19). DISLx[1:0] bits control input data slot length of the SDINx pin. DIDLx[1:0] bits control the input data
word length of the SDINx pin. The slot data format is set by DILSBEx bit.
In stereo mode, DIEDGENx bit should be set to “0” if the data transmission timing of second channel is
LRCK edge basis. In this case, DISLx[1:0] bits setting are ignored.
The SDOUTx output pins of the AK7735 support stereo output mode. Two slots data output is available
for each pin. Each slot data can be assigned by setting SELDOxA[5:0] bits. DOSLx[1:0] bits control
output data slot length of the SDOUTx pin. DODLx[1:0] bits control the output data word length of the
SDOUTx pin. The slot data format is set by DOLSBEx bit.
In stereo mode, DOEDGENx bit must be set to “0” if the data transmission timing of second channel is
LRCK edge basis. In this case, DOSLx[1:0] bits setting are ignored.
Setting example of stereo mode is shown in Table 27.
Mode
0
1
2
3
4
5
Data Format
I²S Compatible
DCFx[2:0]
DILSBEx DIEDGENx DISLx[1:0]
DOLSBEx DOEDGENx DOSLx[1:0]
000
0
0
-
MSB Justified
101
0
0
-
LSB Justified
101
1
0
-
PCM Short Frame
110
0
1
Slot Length
PCM Long Frame
111
0
1
Slot Length
Irregular I²S
000
0
1
Slot Length
Table 27. Stereo Mode Setting Example (-: Do Not Care)
DIDLx[1:0]
DODLx[1:0]
Word Length
Word Length
Word Length
Word Length
Word Length
Word Length
016014707-E-00
- 56 -
2016/12