AK7735EQ Datasheet, PDF (68/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
■ RAM Clear
The AK7735 has a RAM clear function. After a DSP reset release, DRAM and DLRAM are cleared by
“0”. The internal PLL must have stable oscillation before a DSP reset release.
A period of 8/fs (fs: DSP operating sampling rate) is required from a DSP reset release to the RAM clear
start. The required time to clear RAM is about 112µs.
During the RAM clear period, it is possible to send a command to the DSP. (The DSP is stopped during
RAM clear sequence. The sent command is accepted automatically after this sequence is completed.)
PDN(pin)
DxRESETN bit (x=1,2)
DSP1, DSP2
RAM Clear
DSP1, DSP2
Operation Start
Period before RAM Clear Start
(8/fs)
RAM Clear Period (112us)
Figure 49. RAM Clear Sequence
DSP Program Start
Register and RAM settings of the AK7735 are not held if the PDN pin goes to “L”. The DRAM and
DLRAM are not held by a clock reset or a DSP reset.
State
Register PRAM CRAM DRAM DLRAM OFREG
Power Down
(PDN pin = “L”)
x
x
x
x
x
x
Clock Reset
(CKRESETN bit = “0”)
Hold
Hold Hold
x
x
Hold
DSP Reset
(DxRESETN bit = “0”)
Hold
Hold Hold
x
x
Hold
Table 30. Register and RAM Setting Status by Reset (x: Not Hold)
016014707-E-00
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2016/12