AK7735EQ Datasheet, PDF (48/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
3. Clock Sync Domain Setting of Input/output Port
Domain numbers are assigned to each Clock Sync Domain (Table 18). Each input/output port has
setting registers for Clock Sync Domain (Figure 20). Set a domain number to clock sync domain setting
registers for each input/output port. (Table 19, Table 20)
Domain Number Clock Sync Domain
0x0
TieLow
0x1
LRCKSD1, BICKSD1 (SD1)
0x2
LRCKSD2, BICKSD2 (SD2)
0x3
LRCKSD3, BICKSD3 (SD3)
0x4
LRCKSD4, BICKSD4 (SD4)
Table 18. Clock Sync Domain Number
If the output port sync domain setting is in auto mode, the output port inherits the sync domain of the
input data.
e.g.) Data Path Example
It is an example of outputting data from the DAC1 after converting fs=8kHz input data from
the SDIN1 pin to fs=48kHz by SRC (Figure 16). The output port of SRC1 is in auto mode.
Therefore the output port inherits the clock sync domain of SDIN1 input port.
Clock Sync Domain of the SDINx pin is automatically selected by setting EXBCKx[1:0] bits, MSN bit and
SDBCKx[2:0] bits (Table 15, Table 16).
e.g.) Clock sync domain 3 is selected for the SDIN2 pin when EXBCK2[1:0] bits = “011” and
MSN3 bit =“0” (Figure 18).
Figure 18. Clock Sync Domain Setting Example1 of SDINx Pin
e.g.) Clock sync domain 3 is selected for the SDIN1 pin when EXBCK1[1:0] bits = “001”, MSN2
bit =“1” and SDBCK2[2:0] bits = “011” (Figure 19).
Figure 19. S Clock Sync Domain Setting Example2 of SDINx Pin
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