AK7735EQ Datasheet, PDF (66/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
■ Power-down and Reset
1. AK7735 Power-down and Reset Statuses and Power Management
Power-down and power-down release of the AK7735 is controlled by the PDN pin. After power-down is
released, the power management and reset of the AK7735 are controlled by registers such as
CKRESETN bit (Clock Reset), HRESETN bit (HUB Reset), D1RESETN and D2RESETN bits (DSP
reset), CRESETN bits (CODEC Reset) and power management bits for each block.
There are three states for the AK7735 other than normal operation: Power-down, Clock Reset and
System Reset.
1) The power-down state means the status that the PDN pin is “L”. In this state, all blocks of the
AK7735 stop the operation.
2) The clock reset state means the status that the PDN pin is “H” and CKRESETN bit is “0”. In this
state, the DSP, ADC, DAC and SRC blocks are not in operation because the PLL circuit and internal
clocks are stopped.
3) The system reset state means the status that the PDN pin is “H”, CKRESETN bit is “1”, HRESETN
bit is “0”, CRESETN bit is “0” and DxRESETN bit (x= 1, 2) is “0”. In this state, the DSP, ADC, DAC
and SRC blocks are not in operation although the PLL circuit and internal clocks are started. The
system reset is released by setting either HRESETN bit or CRESETN bit or DxRESETN bit (x=1, 2)
to “1”.
Setting
State
PDN CKRESETN DxRESETN HRESETN CRESETN
pin
bit
bit (x=1, 2)
bit
bit
Power-down
L
x
x
x
x
Clock Reset
H
0
0
0
0
System Reset
* 59
H
1
0
0
0
System Reset Release * 60
H
1
1
1
1
Table 29. Reset State Definitions of the AK7735 (x: Don’t Care)
Notes
* 59. A stable clock should be supplied before releasing clock reset (CKRESETN bit = “1”).
* 60. The system reset is released by setting either HRESETN bit or CRESETN bit or DxRESETN bit
(x=1, 2) to “1”.
2. Power-down
The AK7735 can be powered down by bringing the PDN pin = “L”. Power-down status of output pins is
shown in Table 3.
3. Power-down Release
The REF generation circuit (reference voltage source) and a power supply circuit for internal digital
circuit are powered-up by bringing the PDN pin to “H” from “L” after an interval of 600ns or more when
AVDD, LVDD, TVDD and VDD33 are powered up. Control register settings should be made with an
interval of 1ms or more after setting the PDN pin = “H”.
016014707-E-00
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2016/12