AK7735EQ Datasheet, PDF (35/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
■ SPI Interface
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
AVSS=DVSS1=DVSS2=DVSS3=0V; C_L=20pF)
1. SPI Low Speed Mode
Parameter
μP Interface Signal
SCLK Frequency * 49
SCLK Low-level Width
SCLK High-level Width
Microcontroller → AK7735
CSN High-level Width
From CSN “↑” to PDN “↑”
From PDN “↑” to CSN “↓”
From CSN “↓” to SCLK “↓”
From SCLK “↑” to CSN “↑”
SI Latch Setup Time
SI Latch Hold Time
AK7735 → Microcontroller
Delay Time from SCLK “↓” to SO Output
SO Output Hold Time from SCLK “↑” * 48
Symbol Min.
fSCLK
tSCLKL 160
tSCLKH 160
tWRQH 300
tRST
360
tIRRQ
1
tWSC
300
tSCW
480
tSIS
120
tSIH
120
tSOS
tSOH
120
Typ.
Max.
3.0
120
Unit
MHz
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
2. SPI High Speed Mode
Parameter
Symbol Min.
Typ.
Max.
Unit
μP Interface Signal
SCLK Frequency * 49
fSCLK
6
MHz
SCLK Low-level Width
tSCLKL
72
ns
SCLK High-level Width
tSCLKH
72
ns
Microcontroller → AK7735
CSN High-level Width
tWRQH 150
ns
From CSN “↑” to PDN “↑”
tRST
180
ns
From PDN “↑” to CSN “↓”
tIRRQ
1
ms
From CSN “↓” to SCLK “↓”
tWSC
150
ns
From SCLK “↑” to CSN “↑”
tSCW
240
ns
SI Latch Setup Time
tSIS
60
ns
SI Latch Hold Time
tSIH
60
ns
AK7735 → Microcontroller
Delay Time from SCLK “↓” to SO Output
tSOS
60
ns
SO Output Hold Time from SCLK “↑” * 48
tSOH
60
ns
Notes
* 48. Except when writing the 24th bit (8 bits command + 16 bits address) of the command code. This will
be the 8th bit (8 bits command) with “write preparation data read command (24H, 25H, 26H and
27H)”.
* 49. Dummy command writing for switching to SPI interface from I²C interface and control register
access can always be made in SPI high speed mode (Max. 6MHz). DSP RAM area can be
accessed in SPI low speed mode (Max. 3MHz) in clock reset state (CKRESETN bit = “0”) and can
also be accessed in SPI high speed mode (Max. 6MHz) when PLL is locked (CKRESETN bit = “1”
and PLL is locked). It is necessary to set DLRDY bit to “1” when accessing to the DSP RAM area
while PLL is unlocked (Figure 47).
016014707-E-00
- 35 -
2016/12