AK7735EQ Datasheet, PDF (111/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
Case 2
Input Clock
SRCIx
Output Clock
PMSRCx bit
(Internal state) Power-down
SRCOx
(No Clock)
(Don’t care)
(Don’t care)
Clock unstable
“0” data
Input Clocks
Input Data
Output Clocks
Don’t care
Don’t care
Don’t care
< 21ms
Clock stable
Normal
operation
Power-down
Normal data “0” data
SRCxLOCK
Figure 80. SRC Reset Example 2
5. SRC Clock Change
5-1. Internal Reset Function for Clock Change
The SRC block executes internal reset automatically when an input or output clock is stopped. Normal
data will be output within 21ms after the clock is restarted.
5-2. Clock Change Sequence
A clock change sequence of SRC is shown in Figure 81.
Clock
state 1
(input or output)
(unknown) state 2
PMSRCx bit
(interlal state)
normal operation ^Power
down
< 21ms
Clock stable
normal operation
SRCOx
normal data
* 81
normal data
SMUTEx bit
(Recommended * 82 )
0dB
Att.Level
-dB
1024/fso
1024/fso
Figure 81. SRC Clock Change Sequence
Notes
* 81. The data on SRC output may cause a clicking noise. To prevent this, input “0” data to SRC input
(SRCIx) before PMSRCx bit (x= 1, 2) is set to “0”, that will keep the data on SRC output as “0”.
* 82. This click noise (* 81) can also be removed by setting SMUTEx bit (x= 1, 2).
016014707-E-00
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2016/12