AK7735EQ Datasheet, PDF (119/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
001F SDOUT1A Output Data Select
0
0
SELDO1A[5:0]
0020 SDOUT1B Output Data Select
0
0
SELDO1B[5:0]
0021 SDOUT1C Output Data Select
0
0
SELDO1C[5:0]
0022 SDOUT1D Output Data Select
0
0
SELDO1D[5:0]
0023 SDOUT2A Output Data Select
0
0
SELDO2A[5:0]
0024 SDOUT2B Output Data Select
0
0
SELDO2B[5:0]
0025 SDOUT2C Output Data Select
0
0
SELDO2C[5:0]
0026 SDOUT2D Output Data Select
0
0
SELDO2D[5:0]
0027 SDOUT3A Output Data Select
0
0
SELDO3A[5:0]
0028 SDOUT3B Output Data Select
0
0
SELDO3B[5:0]
0029 SDOUT3C Output Data Select
0
0
SELDO3C[5:0]
002A SDOUT3D Output Data Select
0
0
SELDO3D[5:0]
002B SDOUT4A Output Data Select
0
0
SELDO4A[5:0]
002C SDOUT4B Output Data Select
0
0
SELDO4B[5:0]
002D SDOUT4C Output Data Select
0
0
SELDO4C[5:0]
002E SDOUT4D Output Data Select
0
0
SELDO4D[5:0]
002F DAC1 Input Data Select
0
0
SELDA1[5:0]
0030 DAC2 Input Data Select
0
0
SELDA2[5:0]
0031 DSP1 DIN1 Input Data Select
0
0
D1SELDI1[5:0]
0032 DSP1 DIN2 Input Data Select
0
0
D1SELDI2[5:0]
0033 DSP1 DIN3 Input Data Select
0
0
D1SELDI3[5:0]
0034 DSP1 DIN4 Input Data Select
0
0
D1SELDI4[5:0]
0035 DSP1 DIN5 Input Data Select
0
0
D1SELDI5[5:0]
0036 DSP1 DIN6 Input Data Select
0
0
D1SELDI6[5:0]
0037 DSP2 DIN1 Input Data Select
0
0
D2SELDI1[5:0]
0038 DSP2 DIN2 Input Data Select
0
0
D2SELDI2[5:0]
0039 DSP2 DIN3 Input Data Select
0
0
D2SELDI3[5:0]
003A DSP2 DIN4 Input Data Select
0
0
D2SELDI4[5:0]
003B DSP2 DIN5 Input Data Select
0
0
D2SELDI5[5:0]
003C DSP2 DIN6 Input Data Select
0
0
D2SELDI6[5:0]
003D SRC1 Input Data Select
0
0
SELSRCI1[5:0]
003E SRC2 Input Data Select
0
0
SELSRCI2[5:0]
R/W
R/W
R/W
R/W
Default
0
0
00H
SELxxxx[5:0]/D1SELxxxx[5:0]/D2SEL[5:0]: Source Data Select of Each Port (Table 19, Table 20)
Default: 00H (ALL0)
Addr
0041
Register Name
Clock Format Setting 1
R/W
Default
D7
BCKP1
R/W
0
D6
D5
D4
DCF1[2:0]
R/W
000
BCKP1: Relationship of LRCK1 and BICK1 Edges (Table 22)
0: LRCK1 Starts on a BICK1 Falling Edge (default)
1: LRCK1 Starts on a BICK1 Rising Edge
DCF1[2:0]: LRCK1/BICK1 Clock Format Setting (Table 21)
Default: “000” (I²S Mode)
BCKP2: Relationship of LRCK2 and BICK2 Edges (Table 22)
0: LRCK2 Starts on a BICK2 Falling Edge (default)
1: LRCK2 Starts on a BICK2 Rising Edge
DCF2[2:0]: LRCK2/BICK2 Clock Format Setting (Table 21)
Default: “000” (I²S Mode)
D3
BCKP2
R/W
0
D2
D1
D0
DCF2[2:0]
R/W
000
016014707-E-00
- 119 -
2016/12