AK7735EQ Datasheet, PDF (93/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
Sampling mode of DLRAM BANK 0 for the DSP1 and DSP2 are controlled by D1SS[1:0] bits and
D2SS[1:0] bits, respectively.
Mode
D1SS[1:0] bits
D2SS[1:0] bits
Sampling Mode of DLRAM BANK 0
0
00
Update Address in Every Sampling
(default)
1
01
Update Address in Every 2 Samplings
2
10
Update Address in Every 4 Samplings
3
11
Update Address in Every 8 Samplings
Table 43. DLRAM BANK0 Sampling Mode setting of DSP1/DSP2
The DSP1 and DSP2 are able to generate a trigonometric COS table for trigonometric processing. Input
1/4 cycle data of the COS table to CRAM and the DSP generates rest of 3/4 cycle data automatically.
COS table length for CRAM input is variable according to the cycle resolution setting. The cycle
resolution of DSP1 and DSP2 is controlled by D1WAVP[2:0] bits and D2WAVP[2:0] bits, respectively.
Mode
D1WAVP[2:0] bits
D2WAVP[2:0] bits
Cycle Resolution
COS Table Length
0
000
128 points
33 word
(default)
1
001
256 points
65 word
2
010
512 points
129 word
3
011
1024 points
257 word
4
100
2048 points
513 word
5
101
4096 points
1025 word
6
110
N/A
N/A
7
111
N/A
N/A
Table 44. Cycle Resolution Setting of Trigonometric Table for DSP1/DSP2 (N/A: Not Available)
2. Soft SRC Function
DOUT1 port of DSP1 has a built-in FIFO to realize synchronous SRC program for sampling rate
conversion. The output data of DOUT1 port of DSP1 can be up sampled by the FIFO.
A DSP filtering process is necessary when using the soft SRC function. The soft SRC is capable of
integral multiple conversion of a sampling rate between two synchronized clock sync domains,
supporting 6 times up sampling at maximum.
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
Up Sampling
(6 word FIFO x2)
DSP1
Figure 69. DSP1 Soft SRC Function
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
016014707-E-00
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2016/12