AK7735EQ Datasheet, PDF (41/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
The clock source of internal dividing clock MBICKx is selected by CKSx[2:0] bits (Table 8). MBICKx is
generated by dividing the selected clock source according to the BDVx[9:0] bits setting (Table 9).
Additionally, MLRCKx is generated by dividing this MBICKx according to the SDVx[2:0] bits setting
(Table 10).
CKSx[2:0] bits
Clock Source
000
TieLow
(default)
001
PLLMCLK
010
XTI pin
011
BICK1 pin
100
BICK2 pin
101
BICK3 pin
Others
N/A
Table 8. Clock Source of Internal Dividing Clock (N/A: Not Available)
BDVx[9:0] bits
Divide by
0x000
1
0x001 – 0x1FF
BDVx+1
Table 9. MBICKx Setting
(default)
SDVx[2:0] bits
Divide by
000
64
(default)
001
48
010
32
011
128
100
256
Others
N/A
Table 10. MLRCKx Setting (N/A: Not Available)
Clock Sync Domain settings when PLLMCLK is selected as the clock source are shown in Table 11.
When PLLMCLK is selected as the clock source, frequency settings other than shown in Table 11 are
not available. Reference clocks for each setting are calculated as below.
PLLMCLK = 147.456MHz (48kHz base)/ 135.4752MHz (44.1kHz base)
MBICKx = PLLMCLK divided by BDVx[9:0] bits setting
MLRCKx = MBICKx divided by SDVx[2:0] bits setting
ex) When PLLMCLK = 147.456MHz, BDVx[9:0] bits = 0x02F(divide by 48) and SDVx[2:0] bits =
“000”(divide by 64), MBICKx = 147.456MHz/48 = 3.072MHz, MLRCKx = 3.072MHz/64 =
48kHz.
016014707-E-00
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2016/12