AK7735EQ Datasheet, PDF (116/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
■ Register Definitions
Addr
0000
Register Name
System Clock Setting 1
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
REFSEL[1:0]
REFMODE[4:0]
R/W
R/W
R/W
0
00
00H
REFSEL[1:0]: PLL Reference Clock Input Pin Setting (Table 4)
Default: “00” (XTI)
REFMODE[4:0]: PLL Reference Clock Frequency Setting (Table 5)
Default: 00H (256kHz)
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
0001 System Clock Setting 2
CKRESETN 0
0
FSMODE[4:0]
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
00H
CKRESETN: Clock Reset
0: Clock Reset (default)
1: Clock Reset Release
FSMODE[4:0]: Operation Sampling Frequency Mode Setting for Analog Block (Table 12)
Default: 00H (ADC2, DAC1, DAC2=8kHz, ADC1=8kHz)
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
0002 Mic Bias Power Management
0
0
0
0
0
0
0
PMMB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
PMMB: Power Management Setting for MIC Bias Output
0: Power-Off (default)
1: Normal Operation
Addr
0003
0004
0005
0006
0007
0008
0009
000A
Register Name
Sync Domain 1 Setting 1
Sync Domain 1 Setting 2
Sync Domain 2 Setting 1
Sync Domain 2 Setting 2
Sync Domain 3 Setting 1
Sync Domain 3 Setting 2
Sync Domain 4 Setting 1
Sync Domain 4 Setting 2
R/W
Default
D7
D6
BDV1[9] BDV1[8]
BDV2[9] BDV2[8]
BDV3[9] BDV3[8]
BDV4[9] BDV4[8]
R/W
R/W
0
0
D5
D4
D3
CKS1[2:0]
BDV1[7:0]
CKS2[2:0]
BDV2[7:0]
CKS3[2:0]
BDV3[7:0]
CKS4[2:0]
BDV4[7:0]
R/W
R/W
R/W
0
0
0
D2
D1
D0
SDV1[2:0]
SDV2[2:0]
SDV3[2:0]
SDV4[2:0]
R/W
R/W
R/W
0
0
0
CKSx[2:0]: Internal Divider Clock Source Setting of Sync Domain x (Table 8)
Default: “000” (TieLow)
SDVx[2:0]: MLRCK Divider Setting of Sync Domain x (Table 10)
Default: “000” (Divided by 64)
BDVx[9:0]: MBICK Divider Setting of Sync Domain x (Table 9)
Default: 000H (Divided by 1)
016014707-E-00
- 116 -
2016/12