AK7735EQ Datasheet, PDF (73/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
1-2. Read
Command Address Data Length
Description
24H
0bit
16bit + 24bit x n Read CRAM write preparation data of DSP1
25H
0bit
16bit + 24bit x n Read OFREG write preparation data of DSP1
26H
0bit
16bit + 24bit x n Read CRAM write preparation data of DSP2
27H
0bit
16bit + 24bit x n Read OFREG write preparation data of DSP2
32H
16bit
24bit x n
Read operation from OFREG of DSP1 (during DSP reset)
33H
16bit
24bit x n
Read operation from OFREG of DSP2 (during DSP reset)
34H
16bit
24bit x n
Read operation from CRAM of DSP1 (during DSP reset)
35H
16bit
24bit x n
Read operation from CRAM of DSP2 (during DSP reset)
38H
16bit
40bit x n
Read operation from PRAM of DSP1 (during DSP reset)
39H
16bit
40bit x n
Read operation from PRAM of DSP2 (during DSP reset))
40H
16bit
8bit x n
Sequential Control Register Read
40H
16bit
8bit
Device Identification No.
(recognized as Register: Address = 0100H)
40H
16bit
8bit
Device Revision No.
(recognized as Register: Address = 0101H)
72H
16bit
16bit
CRC result Read
0 address should be written.
Sequential Read operation from MIR of DSP1. (max. 8)
76H
16bit
32bit x n
0 address should be written. 28bits are upper-bit justified.
Lower 4 bits are for validity flags. Valid at “0000”. * 64
Sequential Read operation from MIR of DSP2. (max. 8)
77H
16bit
32bit x n
0 address should be written. 28bits are upper-bit justified.
Lower 4 bits are for validity flags. Valid at “0000”. * 64
Note
* 64. Lower 4 bits for validity flags are common in eight MIR data. If the MIR data is updated by a DSP
program, all eight data flags become “0000”. If an MIR read command by a microcontroller is
executed, all eight data flags become “1111”.
When accessing RAM or control registers, data may be read from sequential address locations by
reading data continuously. Reading other than the above-mentioned command code is prohibited.
016014707-E-00
- 73 -
2016/12