C515C_9711 Datasheet, PDF (78/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515C
6.1.1.3.3 Hardware Power Down Mode
Figure 6-12 shows the port 5 structure when the HWPD-pin becomes active (HWPD='0'). First of all
the SFRs are written with their reset values. Therefore, the bit PMOD is cleared (PMOD=0), quasi-
bidirectional port structure is enabled after leaving the hardware power down mode) and the port 5
latch and its direction latch contain a '1' (QPL = '0', QDL='1'). Then the hardware power down mode
with port 5 in tri-state status is entered.
Delay = 1 State
=1
V_CC
1 _"1"
p1 ^"1"
p2 ^"1"
p3
QPL ^"0"
1
& _{"0" n1}
Tristate Port
Pin
QDL ^"1"
PMOD ^"0"
HWPD ^"0"
&
1
V_SS
=1
p5
TTL
=1
&
&
n2
QPL : Port Latch, Output Q
QDL : Direction Latch, Output Q
=1
V_SS
MCS02653
Figure 6-12
Bidirectional Port Structure - Hardware Power Down Mode
Due to HWPD='0' the FET n2 becomes active and the FETs p2 and p5 are switched off. The FETs
p1, p3 and n1 are switched off caused by the status of the port latch, direction latch and of PMOD
(reset values).
Semiconductor Group
6-15
1997-11-01