C515C_9711 Datasheet, PDF (208/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Fail Save Mechanisms
C515C
8 Fail Safe Mechanisms
The C515C offers enhanced fail safe mechanisms, which allow an automatic recovery from
software upset or hardware failure :
– a programmable watchdog timer (WDT), with variable time-out period from 512 µs up to
approx. 1.1 s at 6 MHz.
– an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the
microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.
8.1 Programmable Watchdog Timer
To protect the system against software upset, the user’s program has to clear this watchdog within
a previously programmed time period. lf the software fails to do this periodical refresh of the
watchdog timer, an internal hardware reset will be initiated. The software can be designed so that
the watchdog times out if the program does not work properly. lt also times out if a software error is
based on hardware-related problems.
The watchdog timer in the C515C is a 15-bit timer, which is incremented by a count rate of f_OSC/12
up to f_OSC/192. The system clock of the C515C is divided by two prescalers, a divide-by-two and a
divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bit of the
watchdog timer can be written. Figure 8-1 shows the block diagram of the watchdog timer unit.
f _OSC /6
÷2
÷16
0
7
WDTL
WDT Reset Request
IP0 (A9 _H)
- WDTS - - - - - -
14
8
WDTH
External HW Reset
External HW Power-Down
PE/SWD
WDTPSEL
Control Logic
76
0
- WDT -
-
-
-
-
- IEN0 (A8H)
- SWDT -
-
-
-
-
- IEN1 (B8H)
WDTREL (86H)
MCB02755
Figure 8-1
Block Diagram of the Programmable Watchdog Timer
Semiconductor Group
8-1
1997-11-01