C515C_9711 Datasheet, PDF (168/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515C
resuming normal operation. At the end of the busoff recovery sequence, the error management
counters will be reset.
During the waiting time after the resetting of INIT, each time a sequence of 11 recessive bits has
been monitored, a Bit0Error code is written to the control register, enabling the microcontroller to
check up whether the CAN bus is stuck at dominant or continously disturbed and to monitor the
proceeding of the busoff recovery sequence.
6.5.5 Configuration of the Bit Timing
According to the CAN specification, a bit time is subdivided into four segments (see figure 6-50).
Each segment is a multiple of the time quantum tq. The synchronization segment (Sync-Seg) is
always 1 tq long. The propagation time segment and the phase buffer segment1 (combined to
Tseg1) defines the time before the sample point, while phase buffer segment2 (Tseg2) defines the
time after the sample point. The length of these segments is programmable (except Sync-Seg).
Note : For exact definition of these segments please refer to the CAN specification.
Sync-
Seg
1 Bit Time
TSeg1
TSeg2
Sync-
Seg
1 Time Quantum
(t_q)
Figure 6-50
Bit Timing Definition
Sample
Point
Transmit
Point
MCT02745
The bit time is determined by the C515C clock period CLP (see AC characteristics), the Baud Rate
Prescaler, and the number of time quanta per bit:
bit time
tSync-Seg
tTSeg1
tTSeg2
tq
= tSync-Seg + tTSeg1 + tTSeg2
= 1 • tq
= ( TSEG1 + 1 ) • tq
(= min. 4 • tq)
= ( TSEG2 + 1 ) • tq
(= min. 3 • tq)
= ( BRP + 1 ) • CLP
(= min. CLP)
TSEG1, TSEG2, and BRP are the programmed numerical values from the respective fields of the
Bit Timing Register.
Semiconductor Group
6-105
1997-11-01