C515C_9711 Datasheet, PDF (65/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515C
Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each
of the 7 digital I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop,
which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU.
The Q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from
the CPU. The level of the port pin self is placed on the internal bus in response to a "read-pin" signal
from the CPU. Some instructions that read from a port activate the "read-port-latch" signal, while
others activate the "read-port-pin" signal.
Quasi Bidirectional : TTL Level
Bidirectional : CMOS Level
Read Port Latch
Internal Bus
Write to Latch
D
Q
Port
&
Latch
CLK Q
Port
Driver
Port
Circuitry
Pin
Read Port Pin
Read Direction Latch
Write to IP1
D
Q
PDIR
R
Q
D
Q
Direction
&
Latch
CLK Q
PMOD
Q = 0 : Output
Q = 1 : Input
Bidirectional Port
Control Logic
Delay = 2.5 Machine Cycles
MCS02648
Figure 6-1
Basic Structure of a Port Circuitry
The shaded area in figure 6-1 shows the control logic of the C515C port 5 circuitry, which has been
added to the functionality of the standard 8051 digital I/O port structure. This control logic is used
to provide the additional bidirectional port 5 structure with CMOS voltage levels.
Semiconductor Group
6-2
1997-11-01