C515C_9711 Datasheet, PDF (135/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515C
Bit
CPOL
CPHA
BRS2,
BRS1,
BRS0
Function
Clock polarity
This bit controls the polarity of the shift clock and in conjunction with the CPHA bit
which clock edges are used for sample and shift.
CPOL=0 : SCLK idle state is low.
CPOL=1 : SCLK idle state is high.
Clock phase
This bit controls in conjunction with the CPOL bit controls which clock edges are
used for sample and shift
CPHA=0 : The first clock edge of SCLK is used to sample the data, the second
to shift the next bit out at STO.
In master mode the transmitter will provide the first data bit on STO
immediately after the data was written into the STB register.
In slave mode the transmitter (if enabled via TEN) will shift out the
first data bit with the falling edge of SLS .
CPHA=1 : The first data bit is shifted out with the first clock edge of SCLK and
sampled with the second clock edge
Baudrate selection bits
These bits select one of the possible divide factors for generating the baudrate out
of the micrcontroller clock rate fosc . The baudrate is defined by .
Baudrate =
f_OSC
Dividefactor
for BRS (2-0) ≠ 0
=
f_OSC
2 x 2BRS(2-0)
BRS(2-0)
0
1
2
3
4
5
6
7
Divide
Factor
reserved
4
8
16
32
64
128
256
Example:
Baudrate for fosc
= 8 MHz
reserved
2 MBaud
1 MBaud
500 kBaud
250 kBaud
125 kBaud
62.5 kBaud
31.25 kBaud
Note:
SSCCON must be programmed only when the SSC is idle. Modifying the contents of
SSCCON while a transmission is in progress will corrupt the current transfer and will lead
to unpredictable results.
Semiconductor Group
6-72
1997-11-01