C515C_9711 Datasheet, PDF (169/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515C
6.5.5.1 Hard Synchronization and Resynchronization
To compensate phase shifts between clock oscillators of different CAN controllers, any CAN
controller has to synchronize on any edge from recessive to dominant bus level, if the edge lies
between a sample point and the next synchronization segment, and on any other edge, if it itself
does not send a dominant level. If the hard synchronization is enabled (at the start of frame), the bit
time is restarted at the synchronization segment, otherwise, the resynchronization jump width
(SJW) defines the maximum number of time quanta a bit time may be shortened or lengthened by
one resynchronization. The current bit time is adjusted by
tSJW
= ( SJW + 1 ) • tq
Note :SJW is the programmed numerical value from the respective field of the bit timing register.
6.5.5.2 Calculation of the Bit Time
The programming of the bit time according to the CAN specification depends on the desired
baudrate, the CLP microcontroller system clock rate and on the external physical delay times of the
bus driver, of the bus line and of the input comparator. These delay times are summarised in the
propagation time segment tProp, where
tProp
is two times the maximum of the sum of physical bus delay, the
input comparator delay, and the output driver delay rounded up
to the nearest multiple of tq.
To fulfill the requirements of the CAN specification, the following conditions must be met:
tTSeg2 ≥ 3 • tq = Information Processing Time
tTSeg2 ≥ tSJW
tTSeg1 ≥ 4 • tq
tTSeg1 ≥ tSJW + tProp
Note: In order to achieve correct operation according to the CAN protocol the total bit time should
be at least 8 tq, i.e. tTSeg1 + tTSeg2 ≥ 7 tq.
So, to operate with a baudrate of 1 MBit/sec, the CLP frequency has to be at least 8 MHz.
The maximum tolerance for CLP depends on the phase buffer segment1 (PB1), the phase buffer
segment2 (PB2), and the resynchronization jump width (SJW):
df ≤
AND
df ≤
min (PB1, PB2)
2 x (13 x bit time – PB2)
tSJW
20 x bit time
Semiconductor Group
6-106
1997-11-01