C515C_9711 Datasheet, PDF (142/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515C
TX/RX Shift Register
The Transmit / Receive Shift Register holds the destuffed bit stream from the bus line to allow the
parallel access to the whole data or remote frame for the acceptance match test and the parallel
transfer of the frame to and from the Intelligent Memory.
Bit Stream Processor (BSP)
The Bit Stream Processor is a sequencer controlling the sequential data stream between the TX/RX
Shift Register, the CRC Register, and the bus line. The BSP also controls the EML and the parallel
data stream between the TX/RX Shift Register and the Intelligent Memory such that the processes
of reception, arbitration, transmission, and error signalling are performed according to the CAN
protocol. Note that the automatic retransmission of messages which have been corrupted by noise
or other external error conditions on the bus line is handled by the BSP.
Cyclic Redundancy Check Register (CRC)
This register generates the Cyclic Redundancy Check code to be transmitted after the data bytes
and checks the CRC code of incoming messages. This is done by dividing the data stream by the
code generator polynomial.
Error Management Logic (EML)
The Error Management Logic is responsible for the fault confinement of the CAN device. Its
counters, the Receive Error Counter and the Transmit Error Counter, are incremented and
decremented by commands from the Bit Stream Processor. According to the values of the error
counters, the CAN controller is set into the states error active, error passive and busoff.
The CAN controller is error active, if both error counters are below the error passive limit of 128. It
is error passive, if at least one of the error counters equals or exceeds 128.
It goes busoff, if the Transmit Error Counter equals or exceeds the busoff limit of 256. The device
remains in this state, until the busoff recovery sequence is finished.
Additionally, there is the bit EWRN in the Status Register, which is set, if at least one of the error
counters equals or exceeds the error warning limit of 96. EWRN is reset, if both error counters are
less than the error warning limit.
Bit Timing Logic (BTL)
This block monitors the busline input RXDC and handles the busline related bit timing according to
the CAN protocol.
The BTL synchronizes on a recessive to dominant busline transition at Start of Frame (hard
synchronization) and on any further recessive to dominant busline transition, if the CAN controller
itself does not transmit a dominant bit (resynchronization).
The BTL also provides programmable time segments to compensate for the propagation delay time
and for phase shifts and to define the position of the Sample Point in the bit time. The programming
of the BTL depends on the baudrate and on external physical delay times.
Semiconductor Group
6-79
1997-11-01