C515C_9711 Datasheet, PDF (40/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C515C
Table 3-3
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
Addr Register Content Bit 7
after
Reset¹⁾
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CAH CRCL 00H
.7
.6
.5
.4
.3
.2
.1
CBH CRCH 00H
.7
.6
.5
.4
.3
.2
.1
CCH TL2
00H
.7
.6
.5
.4
.3
.2
.1
CDH TH2
00H
.7
.6
.5
.4
.3
.2
.1
D0H²⁾ PSW
00H
CY
AC
F0
RS1 RS0 OV F1
D8H²⁾ ADCON0 00H
BD
CLK ADEX BSY ADM MX2 MX1
D9H ADDATH 00H
.9
.8
.7
.6
.5
.4
.3
DAH ADDATL 00XX- .1
.0
–
–
–
–
–
XXXXB
DBH P6
–
.7
.6
.5
.4
.3
.2
.1
DCH ADCON1 0XXX- ADCL –
–
–
0
MX2 MX1
X000B
E0H²⁾ ACC
00H
.7
.6
.5
.4
.3
.2
.1
E8H²⁾ P4
FFH
RXDC TXDC INT8 SLS STO SRI SCLK
F0H²⁾ B
00H
.7
.6
.5
.4
.3
.2
.1
F8H²⁾ P5
FFH
.7
.6
.5
.4
.3
.2
.1
F8H²⁾ DIR5 ³⁾ FFH
.7
.6
.5
.4
.3
.2
.1
FAH P7
XXXX- –
–
–
–
–
–
–
XXX1B
FCH VR0 ^{4) 5)} C5H
1
1
0
0
0
1
0
FDH VR1 ^{4) 5)} 95H
1
0
0
1
0
1
0
FEH VR2 ^{4) 5) 6)}
.7
.6
.5
.4
.3
.2
.1
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set.
4) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
5) These SFRs are read-only registers (C515C-8E only).
6) The content of this SFR varies with the actual step of the C515C-8E (see also chapter 10-7).
Bit 0
.0
.0
.0
.0
P
MX0
.2
–
.0
MX0
.0
ADST
.0
.0
.0
INT7
1
1
.0
Semiconductor Group
3-17
1997-11-01