C515C_9711 Datasheet, PDF (187/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515C
6.6.5 A/D Converter Calibration
The C515C A/D converter includes hidden internal calibration mechanisms which assure a save
functionality of the A/D converter according to the DC characteristics. The A/D converter calibration
is implemented in a way that a user program which executes A/D conversions is not affected by its
operation. Further, the user program has no control on the calibration mechanism. The calibration
itself executes two basic functions :
– Offset calibration
: compensation of the offset error of the internal comparator
– Linearity calibration : correction of the binary weighted capacitor network
The A/D converter calibration operates in two phases : calibration after a reset operation and
calibration at each A/D conversion. The calibration phases are controlled by a state machine in the
A/D converter. This state machine executes the calibration phases and stores the calibration results
dynamically in a small calibration RAM.
After a reset operation the A/D calibration is automatically started. This reset calibration phase
which takes 3328 f_ADC clocks, alternating offset and linearity calibration is executed. Therefore, at
8 MHz oscillator frequency and with the default after reset prescaler value of 4, a reset calibration
time of approx. 1.66 ms is reached. For achieving a proper reset calibration, the f_ADC prescaler
value must satisfy the condition f_{ADC max} ≤ 2 MHz.
After the reset calibration phase the A/D converter is calibrated according to its DC characteristics.
Nevertheless, during the reset calibration phase single or continuous A/D can be executed. In this
case it must be regarded that the reset calibration is interrupted and continued after the end of the
A/D conversion. Therefore, interrupting the reset calibration phase by A/D conversions extends the
total reset calibration time. If the specified total unadjusted error (TUE) has to be valid for an A/D
conversion, it is recommended to start the first A/D conversions after reset when the reset
calibration phase is finished. When programming the bit ADCL to ´1´ directly after reset (required
for oscillator clocks greater or equal 8 MHz) the clock prescaler ratio ÷8 is selected and therefore
the reset calibration phase will be extended by factor 2.
After the reset calibration, a second calibration mechanism is initiated. This calibration is coupled
to each A/D conversion. With this second calibration mechanism alternatively offset and linearity
calibration values, stored in the calibration RAM, are always checked when an A/D conversion is
executed and corrected if required.
Semiconductor Group
6-124
1997-11-01