C515C_9711 Datasheet, PDF (236/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

OTP Memory Operation
C515C-8E
The basic programming mode is selected by executing the following steps :
– With a stable V_CC and a clock signal applied to the XTAL pins; the RESET and PSEN pins are
set to “0“ level.
– PROG, PALE, PMSEL1 and EA/V_PP are set to “0“ level; PRD, PSEL, and PMSEL0 are set to
“1“ level.
– PSEL is set to from “1“ to “0“ level and thereafter PROG is switched to “1“ level.
– PMSEL1,0 can now be changed; after EA/V_PP has been set to V_IH high level or to V_PP the OTP
memory is ready for access.
The pins RESET and PSEN must stay at static “0“ signal level during the whole programming mode.
With a falling edge of PSEL the logic state of PROG and EA/V_PP is internally latched. These two
signals are now used as programming write pulse signal (PROG) and as programming voltage input
pin V_PP. After the falling edge of PSEL, PSEL must stay at “0“ state during all programming
operations.
Note: If protection level 1 to 3 has been programmed (see section 10.6) and the programming mode
has been left, it is no more possible to enter the programming mode !
10.4.2 OTP Memory Access Mode Selection
When the C515C-8E has been put into the programming mode using the basic programming mode
selection, several access modes of the OTP memory programming interface are available. The
conditions for the different control signals of these access modes are listed in table 10-2.
Table 10-2
Access Modes Selection
Access Mode
EA/
V_PP ^PROG
Program OTP memory byte V_PP
Read OTP memory byte
V_IH
H
Program OTP lock bits
V_PP
Read OTP lock bits
V_IH
H
Read OTP version byte
V_IH
H
PRD
H
PMSEL
10
HH
HH L
LH
Address
(Port 2)
Data
(Port 0)
A0-7
A8-15
D0-7
–
D1,D0 see
table 10-3
Byte addr.
of version byte
D0-7
The access modes from the table above are basically selected by setting the two PMSEL1,0 lines
to the required logic level. The PROG and PRD signal are the write and read strobe signal. Data is
transferred via port 0 and addresses are applied to port 2.
The following sections describe the details of the different access modes.
Semiconductor Group
10-6
1997-11-01