C515C_9711 Datasheet, PDF (223/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Power Saving Modes
C515C
When the software power down mode wake-up capability has been enabled (bit EWPD in SFR
PCON1 set) prior to entering software power down mode, the software power down mode can be
exit via INT0 while executing the following procedure :
1. In software power down mode pin P3.2/INT0 must be held at high level.
2. Software power down mode is left when P3.2/INT0 goes low for at least 10 µs (latch phase). After
this delay the internal RC oscillator and the on-chip oscillator are started, the state of pin P3.2/
INT0 is internally latched, and P3.2/INT0 can be set again to high level if required. Thereafter,
the oscillator watchdog unit controls the wake-up procedure in its start-up phase.
3. The oscillator watchdog unit starts operation. When the on-chip oscillator clock is detected for
stable nominal frequency, the microcontroller starts again with its operation initiating the software
power down wake-up interrupt. The interrupt address of the first instruction to be executed after
wake-up is 007BH.
4. After the RETI instruction of the software power down wake-up interrupt routine has been
executed, the instruction which follows the initiating power down mode double instruction
sequence will be executed. The peripheral units timer 0/1/2, SSC, CAN controller, and WDT are
frozen until end of phase 4.
All interrupts of the C515C are disabled from phase 2) until the end of phase 4). Other Interrupts
can be first handled after the RETI instruction of the wake-up interrupt routine. If e.g pin P3.2/INT0
is still at low level at the end of phase 4), an external interrupt 0 interrupt routine will be processed
after the RETI instruction of the software power down wake-up interrupt routine (if the external
interrupt 0 was enabled before by setting bit EX0 in SFR IEN0).
9.5 State of Pins in Software Initiated Power Saving Modes
In the idle mode and in the software power down mode the port pins of the C515C have a well
defined status which is listed in the following table 9-1. This state of some pins also depends on the
location of the code memory (internal or external).
Table 9-1
Status of External Pins During Idle and Software Power Down Mode
Outputs
ALE
PSEN
PORT 0
PORT2
PORT1, 3, 5
PORT 5
P7.0
Last Instruction Executed from
Internal Code Memory
Idle
Power Down
High
Low
High
Low
Data
Data
Data
Data
Data /
Data /
alternate outputs last output
Data
Data
Data
Data
Last Instruction Executed from
External Code Memory
Idle
Power Down
High
Low
High
Low
Float
Float
Address
Data
Data /
Data /
alternate outputs last output
Data
Data
Data
Data
Semiconductor Group
9-8
1997-11-01