C515C_9711 Datasheet, PDF (222/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Power Saving Modes
C515C
9.4.2 Exit from Software Power Down Mode
If software power down mode is exit via a hardware reset, the microcontroller with its SFRs is put
into the hardware reset state and the content of RAM and XRAM are not changed. The reset signal
that terminates the software power down mode also restarts the RC oscillator and the on-chip
oscillatror. The reset operation should not be activated before V_CC is restored to its normal
operating level and must be held active long enough to allow the oscillator to restart and stabilize
(similar to power-on reset).
Figure 9-1 shows the procedure which must is executed when software power down mode is left via
the P3.2/INT0 wake-up capability.
In the C515C-8E, the exit from software power down mode procedure can also be triggered through
pin P4.7/RXDC. This pin is selected for the wake-up function when bit WS in SFR PCON1 is set.
The following description refers only to pin P3.2/INT0 but is also valid for pin P4.7/RXDC.
Power Down
Mode
1)
Latch
Phase
2)
Watchdog Circuit
Oscillator Start-up Phase
3)
P3.2/
INT0
10 µs
min.
5 ms typ.
Detailed Timing of Beginning of Phase 4
ALE
PSEN
P2
Invalid Address
P0
Invalid Address/Data
Figure 9-1
Wake-up from Power Down Mode Procedure
Execution of
Interrupt
at 007B _H
4)
RETI Instruction
00 _H
7BH
1st. Instr.
of ISR
MCT03650
Semiconductor Group
9-7
1997-11-01