C515C_9711 Datasheet, PDF (25/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C515C
3.1 Program Memory, "Code Space"
The C515C-8R provides 64 Kbytes of read-only program memory while the C515C-L has no
internal program memory. The C515C-8E provides 64 Kbytes of OTP program memory.. For
internal ROM/OTP program execution the EA pin must be put to high level. The 64K bytes program
memory can also be located completely external. If the EA pin is held low, the C515C fetches all
instructions from an external program memory.
3.2 Data Memory, "Data Space"
The data memory address space consists of an internal and an external memory space. The
internal data memory is divided into three physically separate and distinct blocks : the lower 128
bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area.
While the upper 128 bytes of data memory and the SFR area share the same address locations,
they are accessed through different addressing modes. The lower 128 bytes of data memory can
be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be
accessed through register indirect addressing; the special function registers are accessible through
direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers,
occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through
2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the
internal data memory address space, and the stack depth can be expanded up to 256 bytes.
The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions
that use a 16-bit or an 8-bit address. The internal CAN controller and the internal XRAM are located
in the external address memory area at addresses F700H to FFFFH. Using MOVX instruction with
addresses pointing to this address area, alternatively XRAM and CAN controller registers or
external XRAM are accessed.
3.3 General Purpose Registers
The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose
registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program
status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the
PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines
or interrupt service routines.
The 8 general purpose registers of the selected register bank may be accessed by register
addressing. With register addressing the instruction op code indicates which register is to be used.
For indirect addressing R0 and R1 are used as pointer or index register to address internal or
external memory (e.g. MOV @R0).
Reset initializes the stack pointer to location 07H and increments it once to start from location 08H
which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one
register bank, the SP should be initialized to a different location of the RAM which is not used for
data storage.
Semiconductor Group
3-2
1997-11-01