C515C_9711 Datasheet, PDF (27/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C515C
After a reset operation, bit XMAP0 is reset. This means that the accesses to XRAM and CAN
controller are generally disabled. In this case, all accesses using MOVX instructions within the
address range of F700H to FFFFH generate external data memory bus cycles. When XMAP0 is set,
the access to XRAM and CAN controller is enabled and all accesses using MOVX instructions with
an address in the range of F700H to FFFFH will access internal XRAM or CAN controller.
Bit XMAP0 is hardware protected. If it is reset once (XRAM and CAN controller access enabled) it
cannot be set by software. Only a reset operation will set the XMAP0 bit again. This hardware
protection mechanism is done by an unsymmetric latch at XMAP0 bit. A unintentional disabling of
XRAM and CAN controller could be dangerous since indeterminate values could be read from the
external bus. To avoid this the XMAP0 bit is forced to '1' only by a reset operation. Additionally,
during reset an internal capacitor is loaded. So the reset state is a disabled XRAM and CAN
controller. Because of the load time of the capacitor, XMAP0 bit once written to '0' (that is,
discharging the capacitor) cannot be set to '1' again by software. On the other hand any distortion
(software hang up, noise,...) is not able to load this capacitor, too. That is, the stable status is XRAM
and CAN controller enabled.
The clear instruction for the XMAP0 bit should be integrated in the program initialization routine
before XRAM or CAN controller is used. In extremely noisy systems the user may have redundant
clear instructions.
Semiconductor Group
3-4
1997-11-01