C515C_9711 Datasheet, PDF (57/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Reset / System Clock
C515C
5.2 Hardware Reset Timing
This section describes the timing of the hardware reset signal.
The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2.
Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found
active (low level) the internal reset procedure is started. It needs two machine cycles to put the
complete device to its correct reset state, i.e. all special function registers contain their default
values, the port latches contain 1's etc. Note that this reset procedure is also performed if there is
no clock available at the device. This is done by the oscillator watchdog, which provides an auxiliary
clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins. The RESET signal
must be active for at least one machine cycle. After this time the C515C remains in its reset state
as long as the signal is active. When the reset signal goes inactive this transition is recognized in the
following state 5 phase 2 of the machine cycle. Then the processor starts its address output (when
configured for external ROM) in the following state 5 phase 1. One phase later (state 5 phase 2) the
first falling edge at pin ALE occurs.
Figure 5-2 shows this timing for a configuration with EA = 0 (external program memory). Thus,
between the release of the RESET signal and the first falling edge at ALE there is a time period of
at least one machine cycle but less than two machine cycles.
One Machine Cycle
S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2
P1 P2
RESET
P0
P2
ALE
PCL
INST PCL
OUT
IN OUT
PCH
PCH
OUT
OUT
MCT01821
Figure 5-2
CPU Timing after Reset
Semiconductor Group
5-3
1997-11-01