C515C_9711 Datasheet, PDF (182/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515C
6.6.3 A/D Converter Clock Selection
The ADC uses two clock signals for operation : the conversion clock f_ADC (=1/t_ADC) and the input
clock f_IN (=1/t_IN). f_ADC is derived from the C515C system clock f_OSC which is applied at the XTAL
pins via the ADC clock prescaler as shown in figure 6-53. The input clock f_IN is equal to f_OSC The
conversion f_ADC clock is limited to a maximum frequency of 2 MHz. Therefore, the ADC clock
prescaler must be programmed to a value which assures that the conversion clock does not exceed
2 MHz. The prescaler ratio is selected by the bit ADCL of SFR ADCON1.
The table in figure 6-53 shows the prescaler ratio which must be selected by ADCL for typical
system clock rates. Up to 8 MHz system clock the prescaler ratio 4 is selected. Using a system clock
greater than 8 MHz, the prescaler ratio of 8 must be selected. At system clock frequencies below
8 MHz the prescaler ratio 8 can be used when the maximum performance of the A/D converter is
not necessarily required or the input impedance of the analog source is to high to reach the
maximum accuracy.
ADCL
f _OSC
÷4
MUX
÷8
Clock Prescaler
Conversion Clock f _ADC
Input Clock f _IN
A/D
Converter
Conditions: f _{ADC max} <^_ 2 MHz
f _IN =
f _OSC =
1
CLP
MCS02748
MCU System Clock ADCL
Rate (f_OSC)
2 MHz
0
4 MHz
0
6 MHz
0
8 MHz
0
10 MHz
1
Conversion Clock
f_ADC [MHz]
.5
1
1.5
2
1.25
Figure 6-53
A/D Converter Clock Selection
The duration of an A/D conversion is a multiple of the period of the f_IN clock signal. The calculation
of the A/D conversion time is shown in the next section.
Semiconductor Group
6-119
1997-11-01