C515C_9711 Datasheet, PDF (254/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Device Specifications
C515C
SCLK
STO
SRI
t _SCLK
t _SCL
t _SCH
t_D
t _HD
MSB
t _S t _HI
MSB
TC
LSB
LSB
t _DTC
MCT02417
Notes: Shown is the data/clock relationship for CPOL=CPHA=1. The timing diagram is valid
for the other cases accordingly.
In the case of slave mode and CPHA=0, the output delay for the MSB applies to the
falling edge of SLS (if transmitter is enabled).
In the case of master mode and CPHA=0, the MSB becomes valid after the data has
been written into the shift register, i.e. at least one half SCLK clock cycle before the
first clock transition.
SSC Timing
Semiconductor Group
11-13
1997-11-01