C515C_9711 Datasheet, PDF (170/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515C
6.5.6 CAN Interrupt Handling
The CAN controller has one interrupt output, which is connected with the interrupt controller unit in
the C515C. This interrupt can be enabled/disabled using bit ECAN of SFR IEN2 (further details
about interrupt vector, priority, etc. see chapter 7). Additionally, three bits in the CAN control register
(XX01H) are used to enable specific interrupt sources for interrupt generation.
Since an interrupt request of the CAN-Module can be generated due to different conditions, the
appropriate CAN interrupt status register must be read in the service routine to determine the cause
of the interrupt request. The interrupt identifier INTID (a number) in the interrupt register indicates
the cause of an interrupt. When no interrupt is pending, the identifier will have the value “00”.
If the value in INTID is not “00”, then there is an interrupt pending. If bit IE in the control register is
set, also the interrupt line is activated. The interrupt line remains active until either INTID gets “00”
(ie. the interrupt requester has been serviced) or until IE is reset (ie. interrupts are disabled).
The interrupt with the lowest number has the highest priority. If a higher priority interrupt (lower
number) occurs before the current interrupt is processed, INTID is updated and the new interrupt
overrides the last one.
Table 6-7 below lists the valid values for INTID and their corresponding interrupt sources.
Table 6-7 : Interrupt IDs
INTID
00
01
02
(2+N)
Cause of the Interrupt
Interrupt idle
There is no interrupt request pending.
Status change interrupt
The CAN controller has updated (not necessarily changed) the status register. This
can refer to a change of the error status of the CAN controller (EIE is set and BOFF or
EWRN change) or to a CAN transfer incident (SIE must be set), like reception or
transmission of a message (RXOK or TXOK is set) or the occurrence of a CAN bus
error (LEC is updated). The microcontroller may clear RXOK, TXOK, and LEC,
however, writing to the status partition of the control register can never generate or
reset an interrupt. To update the INTID value the status partition of the control register
must be read.
Message 15 interrupt
Bit INTPND in the message control register of message object 15 (last message) has
been set.
The last message object has the highest interrupt priority of all message objects. ¹⁾
Message N interrupt:
Bit INTPND in the message control register of message object ‘N’ has been set
(N = 1...14). Note that a message interrupt code is only displayed, if there is no other
interrupt request with a higher priority. ¹⁾
1) _{Bit INTPND of the corresponding message object has to be cleared to give messages with a}
lower priority the possibility to update INTID or to reset INTID to “00” (idle state).
Semiconductor Group
6-107
1997-11-01