C515C_9711 Datasheet, PDF (183/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515C
6.6.4 A/D Conversion Timing
An A/D conversion is internally started by writing into the SFR ADDATL with dummy data. A write
to SFR ADDATL will start a new conversion even if a conversion is currently in progress. The
conversion begins with the next machine cycle, and the BSY flag in SFR ADCON0 will be set.
The A/D conversion procedure is divided into three parts :
– Sample phase (t_S), used for sampling the analog input voltage.
– Conversion phase (t_CO), used for the real A/D conversion (including calibration).
– Write result phase (t_WR), used for writing the conversion result into the ADDAT registers.
The total A/D conversion time is defined by t_ADCC which is the sum of the two phase times t_S and
t_CO. The duration of the three phases of an A/D conversion is specified by their corresponding
timing parameter as shown in figure 6-54.
Start of an
A/D Conversion
BSY Bit
Sample
Phase
Conversion Phase
t_S
t _CO
t _ADCC
A/C Conversion Time Cycle Time
t _ADCC = t _S + t _CO
PS = Prescaler Value
Result is written
into ADDAT
Write Result
Phase
t _WR
t _WR = t _IN
MCT02749
Prescaler Ratio t_S
(=PS)
4
8 × t_IN
8
16 × t_IN
t_CO
40 × t_IN
80 × t_IN
t_ADCC
48 × t_IN
96 × t_IN
Figure 6-54
A/D Conversion Timing
Sample Time t_S:
During this time the internal capacitor array is connected to the selected analog input channel and
is loaded with the analog voltage to be converted. The analog voltage is internally fed to a voltage
comparator. With beginning of the sample phase the BSY bit in SFR ADCON0 is set.
Semiconductor Group
6-120
1997-11-01