C515C_9711 Datasheet, PDF (184/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515C
Conversion Time t_CO:
During the conversion time the analog voltage is converted into a 10-bit digital value using the
successive approximation technique with a binary weighted capacitor network. During an A/D
conversion also a calibration takes place. During this calibration alternating offset and linearity
calibration cycles are executed (see also section 6.6.5). At the end of the calibration time the BSY
bit is reset and the IADC bit in SFR IRCON is set indicating an A/D converter interrupt condition.
Write Result Time t_WR:
At the result phase the conversion result is written into the ADDAT registers.
Figure 6-55 shows how an A/D conversion is embedded into the microcontroller cycle scheme
using the relation 6 × t_IN = 1 instruction cycle. It also shows the behaviour of the busy flag (BSY) and
the interrupt flag (IADC) during an A/D conversion.
Prescaler
Selection MOV ADDATL, #0
1 instruction cycle
Write result cycle
MOV A, ADDATL
ADCL = 0 X-1 X 1 2 3 4 5 6 7 8 9 10 11 12
ADCL = 1 X-1 X 1 2 3 4 5
15 16 17 18 19 20
Start of A/D
conversion cycle
BSY Bit
t _ADCC
A/D Conversion Cycle
Start of next conversion
(in continuous mode)
Write
ADDAT
Cont. conv.
Single conv.
IADC Bit
with ADCL = 0
IADC Bit
with ADCL = 1
First instr. of an
interrupt routine
First instr. of an
interrupt routine
MCT02750
Figure 6-55
A/D Conversion Timing in Relation to Processor Cycles
Depending on the selected prescaler ratio (see figure 6-53), two different relationships between
machine cycles and A/D conversion are possible. The A/D conversion is always started with the
beginning of a processor cycle when it has been started by writing SFR ADDATL with dummy data
or after an high-to-low transition has been detected at P4.0/ADST. The ADDATL write operation
may take one or two machine cycles. In figure 6-55, the instruction MOV ADDATL,#0 starts the A/D
conversion (machine cycle X-1 and X). The total A/D conversion (sample and conversion phase) is
finished with the end of the 8th or 16th machine cycle after the A/D conversion start. In the next
machine cycle the conversion result is written into the ADDAT registers and can be read in the same
cycle by an instruction (e.g. MOV A,ADDATL). If continuous conversion is selected (bit ADM set),
the next conversion is started with the beginning of the machine cycle which follows the write result
cycle.
Semiconductor Group
6-121
1997-11-01