C515C_9711 Datasheet, PDF (53/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

External Bus Interface
C515C
4.7.2 Protected ROM/OTP Mode
If the C515C-8R ROM is protected by mask (or C515C-8E in protection level 1), the ROM/OTP
verification mode 2 as shown in figure 4-5 is used to verify the content of the ROM/OTP. The
detailed timing characteristics of the ROM verification mode is shown in the AC specifications
(chapter 11).
RESET
ALE
Port 0
1. ALE Pulse
after Reset
6 CLP
3 CLP
Latch
Latch
Data for
Addr. 0
P3.5
Inputs: ALE = V_SS
PSEN, EA = V_IH
RESET =
Latch
Data for
Addr. 1
Data for
Addr. X ^.16 -1
Latch
Data for
Addr. X ^.16
Latch
Data for
Addr. X ^.16
Low: Verify Error
High: Verify OK
MCT03648
Figure 4-5
ROM/OTP Verification Mode 2
ROM/OTP verification mode 2 is selected if the inputs PSEN, EA, and ALE are put to the specified
logic levels. With RESET going inactive, the ROM/OTP verification mode 2 sequence is started.
The C515C outputs an ALE signal with a period of 3 CLP and expects data bytes at port 0. The data
bytes at port 0 are assigned to the ROM addresses in the following way :
1. Data Byte =
2. Data Byte =
3. Data Byte =
:
16. Data Byte =
:
content of internal ROM/OTP address 0000H
content of internal ROM/OTP address 0001H
content of internal ROM/OTP address 0002H
content of internal ROM/OTP address 000FH
The C515C does not output any address information during the ROM/OTP verification mode 2. The
first data byte to be verified is always the byte which is assigned to the internal ROM address 0000H
and must be put onto the data bus with the rising edge of RESET. With each following ALE pulse
the ROM/OTP address pointer is internally incremented and the expected data byte for the next
ROM/OTP address must be delivered externally.
Semiconductor Group
4-11
1997-11-01