C515C_9711 Datasheet, PDF (54/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

External Bus Interface
C515C
Between two ALE pulses the data at port 0 is latched (at 3 CLP after ALE rising edge) and compared
internally with the ROM/OTP content of the actual address. If an verify error is detected, the error
condition is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of
the last 16 verify operations is output at P3.5. If P3.5 has been set low (verify error detected), it will
stay at low level even if the following ROM verification sequence does not detect further verify
errors. In ROM/OTP verification mode 2, the C515C must be provided with a system clock at the
XTAL pins.
Figure 4-6 shows an application example of a external circuitry which allows to verify a protected
ROM/OTP inside the C515C in ROM/OTP verification mode 2. With RESET going inactive, the
C515C starts the ROM/OTP verify sequence. Its ALE is clocking an 16-bit address counter. This
counter generates the addresses for an external EPROM which is programmed with the contents of
the internal (protected) ROM/OTP. The verify detect logic typically displays the pass/fail information
of the verify operation. P3.5 can be latched with the falling edge of ALE.
When the last byte of the internal ROM/OTP has been handled, the C515C starts generating a
PSEN signal. This signal or the CY signal of the address counter indicate to the verify detect logic
the end of the internal ROM/OTP verification.
P3.5
Carry
ALE
CLK
16 Bit
2 kΩ
Address
Counter
C515C-8R
R
C515C-8E
&
RESET
Port 0
EA
PSEN
&
V_CC
Verify
Detect
Logic
V_CC
Figure 4-6
ROM Verification Mode 2 - External Circuitry Example
Semiconductor Group
4-12
A0 - A15
Compare
Code
ROM
D0 - D7
CS OE
MCS02720
1997-11-01