C515C_9711 Datasheet, PDF (136/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515C
This register enables or disables interrupt request for the status bits. SCIEN must only be written
when the SSC interrupts are disabled in the general interrupt enable register IEN2 (9AH) using bit
ESSC otherwise unexpected interrupt requests may occur.
Special Function Register SCIEN (Address ACH)
MSB
Bit No. 7
6
5
4
3
ACH
–
–
–
–
–
Reset Value : XXXXXX00B
LSB
2
1
0
– WCEN TCEN SCIEN
Bit
–
WCEN
TCEN
Function
Reserved for future use.
Write collision interrupt enable
WCEN =0 : No interrupt request will be generated if the WCOL bit in the status
register SCF is set.
WCEN=1 : An interrupt is generated if the WCOL bit in the status register SCF is
set.
Transfer completed interrupt enable
TCEN =0 : No interrupt request will be generated if the TC bit in the status
register SCF is set.
TCEN=1 : An interrupt is generated if the TC bit in the status register SCF is set.
Note:
The SSC interrupt behaviour is in addition affected by bit ESSC in the interrupt enable
register IEN2 and by bit 2 in the interrupt priority registers IP0 and IP1.
Semiconductor Group
6-73
1997-11-01