C515C_9711 Datasheet, PDF (233/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

OTP Memory Operation
C515C-8E
10.3 Pin Definitions
The following table 10-1 contains the functional description of all C515C-8E pins which are required
for OTP memory programming.
Table 10-1
Pin Definitions and Functions in Programming Mode
Symbol
RESET
PMSEL0
PMSEL1
Pin Number I/O*) Function
1
I
Reset
This input must be at static “0“ (active) level during the whole
programming mode.
15
I
Programming mode selection pins
16
I
These pins are used to select the different access modes in
programming mode. PMSEL1,0 must satisfy a setup time to the
rising edge of PALE. When the logic level of PMSEL1,0 is
changed, PALE must be at low level.
PMSEL1
0
0
1
1
PMSEL0
0
1
0
1
Access Mode
Reserved
Read version bytes
Program/read lock bits
Program/read OTP memory byte
PSEL
17
PRD
18
PALE
19
XTAL2 36
XTAL1 37
A0/A8 -
A7/A15
38 - 45
*) I = Input
O = Output
I
Basic programming mode select
This input is used for the basic programming mode selection
and must be switched according figure 3.
I
Programming mode read strobe
This input is used for read access control for OTP memory
read, version byte read, and lock bit read operations.
I
Programming address latch enable
PALE is used to latch the high address lines. The high address
lines must satisfy a setup and hold time to/from the falling edge
of PALE. PALE must be at low level whenever the logic level of
PMSEL1,0 is changed.
I
XTAL2
Input to the oscillator amplifier.
O XTAL1
Output of the inverting oscillator amplifier.
I
Address lines
P2.0-7 are used as multiplexed address input lines A0-A7 and
A8-A15. A8-A15 must be latched with PALE.
Semiconductor Group
10-3
1997-11-01