C515C_9711 Datasheet, PDF (26/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C515C
3.4 XRAM Operation
The XRAM in the C515C is a memory area that is logically located at the upper end of the external
memory space, but is integrated on the chip. Because the XRAM is used in the same way as
external data memory the same instruction types (MOVX) must be used for accessing the XRAM.
3.4.1 XRAM/CAN Controller Access Control
Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to XRAM and the CAN
controller. XMAP0 is a general access enable/disable control bit and XMAP1 controls the external
signal generation during XRAM/CAN controller accesses.
Special Function Register SYSCON (Address B1H)
Reset Value C515C-8R : X010XX01B
Reset Value C515C-8E : X010X001B
Bit No. MSB
LSB
7
6
5
4
3
2
1
0
B1H
– PMOD EALE RMAP – _{CSWO XMAP1 XMAP0} SYSCON
The function of the shaded bit is not described in this section.
Bit
–
XMAP1
XMAP0
Function
Not implemented. Reserved for future use.
XRAM/CAN controller visible access control
Control bit for RD/WR signals during XRAM/CAN Controller accesses. If
addresses are outside the XRAM/CAN controller address range or if
XRAM is disabled, this bit has no effect.
XMAP1 = 0 : The signals RD and WR are not activated during accesses to
the XRAM/CAN Controller
XMAP1 = 1 : Ports 0, 2 and the signals RD and WR are activated during
accesses to XRAM/CAN Controller. In this mode, address
and data information during XRAM/CAN Controller accesses
are visible externally.
Global XRAM/CAN controller access enable/disable control
XMAP0 = 0 : The access to XRAM and CAN controller is enabled.
XMAP0 = 1 : The access to XRAM and CAN controller is disabled (default
after reset!). All MOVX accesses are performed via the
external bus. Further, this bit is hardware protected.
When bit XMAP1 in SFR SYSCON is set, during all accesses to XRAM and CAN Controller RD and
WR become active and port 0 and 2 drive the actual address/data information which is read/written
from/to XRAM or CAN controller. This feature allows to check the internal data transfers to XRAM
and CAN controller. When port 0 and 2 are used for I/O purposes, the XMAP1 bit should not be set.
Otherwise the I/O function of the port 0 and port 2 lines is interrupted.
Semiconductor Group
3-3
1997-11-01